Stress released VLSI structure by the formation of porous interm

Details Stress released VLSI structure by the formation of porous interm Stress released VLSI structure by the formation of porous interm

1995-02-13

1996-05-14

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257644, 257758, H01L 2906

Patent

active

055170625

ABSTRACT:
A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer. A second layer of silicon oxide is deposited overlying the spin-on-glass layer to complete formation of the porous intermetal dielectric of the said integrated circuit.

REFERENCES:
patent: 4654269 (1987-03-01), Lehrer
patent: 5099304 (1992-03-01), Takemura et al.
patent: 5119164 (1992-06-01), Sliwa, Jr. et al.
patent: 5278103 (1994-01-01), Mallon et al.
patent: 5302551 (1994-04-01), Iranmanesh et al.

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