Patent
1989-12-21
1992-02-25
MacDonald, Allen R.
G06F 1518
Patent
active
050918648
ABSTRACT:
A neural net signal processor provided with a single layer neural net constituted of N neuron circuits which sums the results of the multiplication of each of N input signals Xj(j=1 to N) by a coefficient mij to produce a multiply-accumulate value ##EQU1## thereof, in which input signals Xj(j=1 to N) for input to the single layer neural net are input as serial input data, comprising: a multiplicity of systolic processor elements SPE-1(i=1 to M), each comprised of a two-state input data delay latch; a coefficient memory; means for multiplying and summing for multiply-accumulate output operations; an accumulator; a multiplexor for selecting a preceding stage multiply-accumulate output Sk(k=1 to i-1) and the multiply-accumulate product Si computed by the said circuit; wherein the multiplicity of systolic processor elements are serially connected to form an element array and element multiply-accumulate output operations are executed sequentially to obtain the serial multiply-accumulate outputs Si(i=1 to M) of one layer from the element array.
REFERENCES:
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P. Andrew Penz, et al., "Digital Signal Processor Accelerators for Neural Network Simulations", American Institute of Physics, 1986, pp. 345-355.
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Baji Toru
Inouchi Hidenori
Hitachi , Ltd.
MacDonald Allen R.
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