Chained addressing mode pipelined processor which merges separat

Details Chained addressing mode pipelined processor which merges separat Chained addressing mode pipelined processor which merges separat

1989-02-22

1992-02-25

Lee, Thomas C.

Boots, shoes, and leggings

3642599, 3642541, 3642621, 3642515, 364DIG1, G06F 935

Patent

active

050918532

ABSTRACT:
A data processor of the present invention adopts a multi-stage indirect (chained) addressing mode, and merges pipeline processing units which are generated with respect to each designation of the chained addressing mode into a pipeline processing unit expressing the operation information for the operand of the instruction after completion of address calculation, thereby processing loads at each stage are equalized and processing speed as a whole apparatus increases.

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