System for fast selection of non-cacheable address ranges using

Details System for fast selection of non-cacheable address ranges using System for fast selection of non-cacheable address ranges using

1990-02-02

1992-02-25

Lee, Thomas C.

Boots, shoes, and leggings

3642434, 36424341, 3642568, 3642449, 3642599, 3649642, 36496577, 364DIG1, 364DIG2, G06F 1200, G06F 1300

Patent

active

050918508

ABSTRACT:
A fast logic system for decoding addresses for the purpose of designating areas of memory as non-cacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

REFERENCES:
patent: 4399503 (1983-08-01), Hawley
patent: 4591975 (1986-05-01), Wade et al.
patent: 4646233 (1987-02-01), Weatherford et al.
patent: 4719568 (1988-01-01), Carrubba et al.
Intel Product Data Book, 82385 High Performance 32-bit Cache Controller.
Intel Product Data Book, 80386 High Performance 32-bit CHMOS Microprocessor.

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