Associated memory computer with floating non-wired cells

Multiplex communications – Wide area network – Packet switching

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H04J 324

Patent

active

049397273

ABSTRACT:
The present multiprocessor computing architecture uses a Host device to communicate directly with each processor of an array. The processors are identical, but initially unindividuated. Each is capable of generating on command an identification indicia, expressable as a number. Using the set of such numbers, the Host executes an interactive initialization protocol, through which each processor assumes a digitially coded address or label related to its generated number. The label thereafter is used by the Host to transmit data or to order data from the so-identified element. One Host-processor configuration uses direct broadcast for communications and, therefore, is not reliant on conventional physical, that is hard-wired, paths. Need to place individual processors in particular locations with respect to one another, or in a predetermined configuration such as a tree, is obviated.

REFERENCES:
patent: 4430651 (1984-02-01), Bryant et al.
patent: 4742516 (1988-05-01), Yamaguchi

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