Simplified processor for digital filter applications

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364736, G06F 1531, G06F 752

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049396846

ABSTRACT:
An arithmetic logic unit (ALU) of a digital processor includes a multiplier to which a first data word A and a second data word B are fed as input data from a data memory. A third data word C, also coming from the data memory, is fed through a barrel shifter, whose shift number is q. The output of the barrel shifter is fed to one input of an adder having its other input connected to the output of the multiplier. The output of the adder provides a fourth data word D, which is written into the data memory. All movements of data necessary to form the fourth data word D are defined of a single program instruction.

REFERENCES:
patent: 4538239 (1985-08-01), Magar
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4598382 (1986-07-01), Sato
Electronic Design, Book 34 (1986) Feb. 20., No. 4, Hasbrouck Heights, N.J., B. Eichen, et al.: "Floating-Point Math Integrated on Chip Makes DSP IC a Standout".
Electronik, Band 35, No. 18, Sep. 5, 1986, pp. 112-118, 121-125, Munchen, Deutschland, R. Gluth: "Integrierte Signalprozessoren".

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