Frequency division network having low phase noise

Details Frequency division network having low phase noise Frequency division network having low phase noise

1990-11-14

1992-02-25

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

328167, 377 42, 377 47, 3072191, H03K 1716, H03K 2140

Patent

active

050916998

ABSTRACT:
A frequency division network is disclosed in which a sinusoidal signal is converted to a digital format for frequency division and then converted back to the sinusoidal format, the sinusoidal output waveform having low phase noise. In a preferred embodiment the frequency conversion takes place in an m-fold plurality of edge triggered flip-flops, connected to divide by two, and clocked by the sinusoidal waveform. Each flip-flop is subject to jitter causing phase noise, which is minimized when the output of two sets of four flip-flops are averaged, and then filtered to obtain the sinusoidal fundamental. When a crystal filter having a very narrow pass band is employed, the phase noise is further reduced. The frequency division network uses low cost components and the phase noise of the output waveform approaches that of a stable crystal oscillator.

REFERENCES:
patent: 3579117 (1971-05-01), Norris et al.
patent: 4288750 (1981-09-01), Newton et al.
patent: 4386321 (1983-05-01), Savage
patent: 4442500 (1984-04-01), Kongable et al.
patent: 4929947 (1990-05-01), Toyama

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