Manufacturing method for semiconductor memories

Details Manufacturing method for semiconductor memories Manufacturing method for semiconductor memories

1991-06-28

1992-04-07

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 357 236, H01L 21265, H01L 2170, H01L 2100

Patent

active

051028204

ABSTRACT:
In a manufacturing method for a dynamic random access memory with box-structured memory cells is disclosed, a polysilicon side wall is again formed inside the polysilicon side wall forming the outer wall. After that, with the side wall formed on this inner wall used as mask, an opening for forming a cavity is made in the center of the storage node in a self-aligned manner.

REFERENCES:
patent: 5049957 (1991-11-01), Inoue et al.
Inoue et al., "A Spreadstacked Capacitor (SSC) Cell for 64 Mbit DRAMs", IEDM, 1989 IEEE, pp. 2.3.1 to 2.3.4.
"A New Stacked Capacitor Cell with a Storage Node Having a Thin Box Structure", by S. Inoue et al., Toshiba Co., 21st SSDM (Solid State Devices and Materials), 1989, pp. 141-144.

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