Staircase sidewall spacer for improved source/drain architecture

Details Staircase sidewall spacer for improved source/drain architecture Staircase sidewall spacer for improved source/drain architecture

1991-03-26

1992-04-07

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 29, 437 30, 437 34, 437 41, 437 56, 437 67, 357 233, H01L 21336, H01L 27092

Patent

active

051028166

ABSTRACT:
Selective etching of a conformal nitride layer overlying a conformal oxide layer and a subsequent etching of the oxide layer provide for a staircase shaped sidewall spacer which is used to align source and drain regions during implantation. Extent of the implanted n-
+ and/or p-/p+ regions within the substrate can be tightly controlled due to the tight dimensional tolerances obtained by the footprint of the spacer. Further the source/drain profiles can be utilized with elevated polysilicon and elevated polysilicon having subsequent salicidation.

REFERENCES:
patent: 3472712 (1969-10-01), Bower
patent: 3475234 (1969-10-01), Kerwin et al.
patent: 3615934 (1971-10-01), Bower
patent: 4072545 (1978-02-01), De La Moneda
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4356040 (1982-10-01), Fu et al.
patent: 4384301 (1983-05-01), Tasch, Jr. et al.
patent: 4488351 (1984-12-01), Momose
patent: 4530150 (1985-07-01), Shirato
patent: 4642878 (1987-02-01), Maeda
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 4728617 (1988-03-01), Woo et al.
patent: 4735916 (1988-04-01), Homma et al.
patent: 4740484 (1988-04-01), Norstrom et al.
patent: 4744859 (1988-05-01), Hu et al.
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4760033 (1988-07-01), Mueller
patent: 4764477 (1988-08-01), Chang et al.
patent: 4808544 (1989-02-01), Matsui
patent: 4818714 (1989-04-01), Haskell
patent: 4818715 (1989-04-01), Chao
patent: 4826782 (1989-05-01), Sachitano et al.
patent: 4837180 (1989-06-01), Chao
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4855247 (1989-08-01), Ma et al.
patent: 4873557 (1989-10-01), Kito
patent: 4998150 (1991-03-01), Rodder et al.
Pfiester, "LDD MOSFET's Using Disposable Sidewall Spacer Technology", IEEE Electron Device Letters, vol. 9, No. 4, Apr. 1988, pp. 189-192.
IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989, "Method for Making Lightly Doped Drain Shallow Junctions", pp. 110-111.
IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun. 1985, "New Scheme to Form Shallow N+ and P+ Junctions for MOS Devices", pp. 366-367.
2244 Research Disclosure (1989) Jul., No. 303, New York, U.S., "Method for Making Devices having Reduced Field Gradients at Junction Edges", p. 496.
1988 Symposium on VLSI Technology, Oh et al., Simultaneous Formation of Shallow-Deep Stepped Source/Drain for Sub-Micron CMOS, May 10-13, 1988, pp. 73-74.
IEEE, Nov. 1989, Lu et al., Submicrometer Salicide CMOS Devices with Self-Aligned Shallow-Deep Junctions, pp. 487-489.
IEEE, Feb. 1985, Matsumoto et al., An Optimized and Reliable LDD Structure for 1-.mu.m NMOSFET Based on Substrate Current Analysis, pp. 429-433.
IEEE, Feb. 1986, Huang et al., A Novel Submicron LDD Transistor with Inverse-T Gate Structure IEDM 86, pp. 742-745.
IEEE, Oct. 1984, Oh and Kim, A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes, pp. 400-402.
IEEE, Jul. 1989, Yamada et al., Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit Drams pp. 2.4.1-2.4.4.

Affiliated with

Also associated with

Rating

Staircase sidewall spacer for improved source/drain architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Staircase sidewall spacer for improved source/drain architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Staircase sidewall spacer for improved source/drain architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1894900