Rate multiplier square root extractor with increased accuracy fo

Details Rate multiplier square root extractor with increased accuracy fo Rate multiplier square root extractor with increased accuracy fo

1982-07-06

1984-09-04

Heyman, John S.

Boots, shoes, and leggings

328143, 364752, G06G 720, G06G 712

Patent

active

044700199

ABSTRACT:
Circuitry for extracting the square root of an incoming voltage signal is disclosed. The circuit (10) utilizes a four-bit up/down counter (14) to control the output duty cycle of a pair of four-bit rate multipliers (16, 18) connected in a cascaded configuration. The output of the second rate multiplier (18), which is related to the square of the up/down counter value, is used to control the mode of the counter (14) so as to track the incoming voltage signal. Inasmuch as the square of the up/down counter value is tracking the incoming voltage signal, the output duty cycle of the first rate multiplier (16) in the cascaded pair is the square root of the incoming voltage signal which is subsequently converted into analog form. The circuit also utilizes a "dithering" technique so that the resulting square root output signal has greater than four-bit accuracy.

REFERENCES:
patent: 3280314 (1966-10-01), Weigler
patent: 3728535 (1973-04-01), Dickman et al.
patent: 4088960 (1978-05-01), Osborne
patent: 4346346 (1982-08-01), Silberberg

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