Patent
1987-08-04
1990-07-03
Clawson, Jr., Joseph E.
357 238, 357 86, H01L 2978
Patent
active
049395718
ABSTRACT:
An insulated-gate type transistor having a semi-conductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped drain region for receiving the carriers supplied from the source region, both of which regions may be provided separately in a main surface of the body, a channel region located between the source and drain regions for the travel of these carriers, an insulated-gate structure inputted with a gate voltage for controlling the travel of those carriers, a semiconductor region formed in the neighborhood of the source region within the body and having a portion located below the source region and another portion extending beyond therefrom toward the drain region and serving to define the channel region and to increase the ratio of the amount of carriers reaching the drain region to the total amount of the carriers supplied from the source region. This transistor can be easily manufactured with a single substrate from that side of the main surface. This transistor is suitable for use in constructing integrated circuits and enables construction of complementary devices.
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P. Richman, "MOS Field Effect Transistors and Integrated Circuits", .COPYRGT.1973, TK 7871.85.R466, Wiley-Interscience, Inc. 86-107.
C. Bertin et al, "Substrate Contact Design," IBM Tech. Discl. Bull. vol. 148, Jan. 1972, 2316.
Nishizawa Jun-ichi
Ohmi Tadahiro
Clawson Jr. Joseph E.
Zaidan Hojin Handotai Kenkyu Shinkokai
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