Trench interconnect for CMOS diffusion regions

Details Trench interconnect for CMOS diffusion regions Trench interconnect for CMOS diffusion regions

1989-01-30

1990-07-03

Carroll, J.

357 231, 357 49, 357 54, 357 59, 357 67, 357 71, H01L 2702, H01L 2978, H01L 2904, H01L 2348

Patent

active

049395670

ABSTRACT:
A sub-surface interconnection structure for coupling an n-type diffusion to a p-type diffusion. The structure is a conductor-filled trench disposed between the diffusion regions. The trench has a thin dielectric layer on its sidewalls and bottom. The conductor within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.

REFERENCES:
patent: 4477310 (1984-10-01), Park et al.
patent: 4503451 (1985-03-01), Lund et al.
patent: 4613886 (1986-09-01), Chwang
patent: 4647957 (1987-03-01), Coquin et al.
patent: 4650544 (1987-03-01), Erb et al.
patent: 4653025 (1987-03-01), Minato et al.
patent: 4661202 (1987-04-01), Ochii
N. Lu et al., "The SPT Cell-A New Substrate-Plate Trench Cell for DRAMS," ISSCC Digest of Technical Papers-1987.

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