Partitioning the processors of a massively parallel single array

Details Partitioning the processors of a massively parallel single array Partitioning the processors of a massively parallel single array

1991-07-01

1992-12-29

Shaw, Gareth D.

Boots, shoes, and leggings

395325, 364DIG1, 3642287, 3642289, 364229, 3642291, 3642294, 3642295, G06F 1516

Patent

active

051758652

ABSTRACT:
A parallel computer comprised of a plurality of identical processors, each processor having control and data inputs and outputs for communication with the host computers and separate interprocessor inputs and outputs for communication between the processors. The processors are permanently interconnected through interprocessor communications routers into a first, single n-cube array for purposes of interprocessor communication. The data and control inputs and outputs of the processors are separately connected in parallel to the host computers through a resource allocation means to divide the first, single n-cube array of processors into a multiplicity of smaller second arrays controlled by selected ones of the host computers. All processors of the parallel computer are and remain interconnected into a single boolean n-cube array for interprocessor communication, regardless of the number or identities of the second arrays connected together to a host computer, and each group of one or more second arrays connected to a host computer appear to the host computer as a single array of processors.

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