Delayed cache write enable circuit for a dual bus microcomputer

Details Delayed cache write enable circuit for a dual bus microcomputer Delayed cache write enable circuit for a dual bus microcomputer

1988-05-26

1992-12-29

Shaw, Gareth D.

Boots, shoes, and leggings

364DIG1, 36424341, 364271, 3642715, 395425, 395550, G06F 1342

Patent

active

051758261

ABSTRACT:
In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

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