Boots – shoes – and leggings
Patent
1992-03-23
1995-10-24
Coleman, Eric
Boots, shoes, and leggings
395375, 3642613, 3642619, 3642629, 364230, 3642301, 364DIG1, G06F 900
Patent
active
054617227
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a parallel processing apparatus comprising an instruction processor for parallelly executing a plurality of instructions and, more particularly, to a parallel processing apparatus suitable for a case wherein a plurality of instructions including at least two branch instructions are parallelly executed.
BACKGROUND ART
In recent years, a processing apparatus, which comprises an instruction processor having n pipeline processing units (n is an integer equal to or larger than 2) for processing instructions has been disclosed. This processing apparatus is called a parallel processing apparatus since it fetches n instructions at a time from an instruction stream of one load module, and parallelly executes-these instructions in the pipeline processing units in the instruction processor. In a parallel processing apparatus of this type, to continuously process n instructions at a time is important to improve its performance. Therefore, when a program is (locally) constituted by instructions independent from each other, the highest processing performance can be obtained.
The most serious problem may arise in parallel execution of instructions in the above-mentioned parallel processing apparatus, if these instructions include branch instructions. For example, assume a case wherein four instructions, i.e., ADD (addition), BR1 (conditional branch), SUB (subtraction), and BR2 (conditional branch) are parallelly executed. It is also assumed that these four instructions are arranged in the order of ADD, BR1, SUB, and BR2 in the program, as shown in FIG. 12. With this arrangement of the instructions, a sequential processing apparatus executes these instructions in the order of ADD .fwdarw.BR1 .fwdarw.SUB .fwdarw.BR2. This sequential execution order is handled as priority of the instructions in the parallel processing apparatus. In this description, assume that the BR1 instruction uses a result Of the ADD instruction as a branch condition, and the BR2 instruction uses a result of a CMP (comparison) instruction executed prior to the ADD instruction as a branch condition.
Since the above-mentioned four instructions include the two branch instructions, i.e., BR1 and BR2, four instructions to be executed next (next instruction string) depend on the results of BR1 and BR2. As possible next instruction strings, the following three cases are available.
(1) When branch condition of BR1 does not hold true, and branch condition of BR2 holds true:
In this case, the next instruction string includes four instructions starting at an MP (multiplication) instruction at a branch target address TAR1 designated by the BR2 instruction, as shown in FIG. 12.
(2) When branch condition of BR1-holds true:
In this case, the next instruction string includes four instructions starting at a DV (division) instruction at a branch target address TAR2 designated by the BR1 instruction, as shown in FIG. 12. Therefore, execution of the SUB and BR2 instructions after the BR1 instruction must be canceled.
(3) When branch conditions of neither BR1 nor BR2 hold true:
In this case, the next instruction string includes four instructions following the BR2 instruction.
As exemplified above, in the parallel processing apparatus, there are various cases of next instruction string fetch processing depending on combinations of true
ot-true results of branch instructions when a single execution step includes a plurality of branch instructions. The next instruction string can only be determined after branch judgment processing of all the plurality of branch instructions is completed.
For this reason, the conventional parallel processing apparatus waits for completion of branch judgment processing of all the branch instructions to be parallelly executed and, thereafter, checks the branch judgment results and the priority levels of the branch instructions so as to determine the next instruction string, and then fetches the next instruction string. However, since it is troublesome to check the branch judgment resul
REFERENCES:
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4926323 (1990-05-01), Baror et al.
patent: 5121488 (1992-06-01), Ngai
Coleman Eric
Kabushiki Kaisha Toshiba
Nguyen Dzung C.
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