Frequency divider with reduced clock skew

Details Frequency divider with reduced clock skew Frequency divider with reduced clock skew

1991-10-08

1992-12-29

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 28, 377114, 3072471, H03K 2108

Patent

active

051757524

ABSTRACT:
A first frequency dividing circuit receives an input clock signal from an input terminal and divides the frequency of the input clock signal to produce a first signal which it supplies to an output terminal. A second frequency dividing circuit divides the frequency of the input clock signal to produce a second signal having the same frequency as the first signal but differing from the first signal in phase. The second signal controls a gating circuit. When switched on, the gating circuit connects the output terminal to the input terminal, or to an auxiliary power-supply or ground terminal, thereby deskewing the signal at the output terminal.

REFERENCES:
patent: 3902125 (1975-08-01), Oliva
patent: 4281259 (1981-07-01), Ozawa
patent: 4348640 (1982-09-01), Clendening
patent: 4366394 (1982-12-01), Clendening et al.

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