Fishing – trapping – and vermin destroying
Patent
1990-11-01
1992-02-25
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 41, 437 48, 437909, 148DIG105, H01L 2144, H01L 21265
Patent
active
050913379
ABSTRACT:
A method for manufacturing an amorphous silicon thin film transistor in which a gate insulating layer is provided over a gate on a substrate. An amorphous silicon layer is formed on the gate insulating layer, and a protective insulating layer is formed on the amorphous silicon layer. A pattern conforming to the gate is applied to the protective layer, and the amorphous layer is exposed in regions outside of the pattern. A doped silicon layer is then added, and source and drain electrodes formed to partly overlap the remaining protective insulating layer.
REFERENCES:
patent: 4587720 (1986-05-01), Chenevas-Paule et al.
patent: 4715930 (1987-12-01), Diem
Tanaka Sakae
Watanabe Yoshiaki
Hearn Brian E.
Nguyen Tuan
Seikosha Co. Ltd.
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