Discrete time control loop method for clocking data in an asynch

Details Discrete time control loop method for clocking data in an asynch Discrete time control loop method for clocking data in an asynch

1994-02-23

1995-10-24

Chin, Stephen

Pulse or digital communications

Synchronizers

375371, 360 51, H04L 700

Patent

active

054616387

ABSTRACT:
A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

REFERENCES:
patent: 4433424 (1984-02-01), Taber et al.
patent: 4797845 (1989-01-01), Stikvoort
patent: 4841551 (1989-06-01), Avaneas
patent: 4912729 (1990-03-01), Van Rens et al.
patent: 4987373 (1991-01-01), Soo
patent: 5001724 (1991-03-01), Birgenbeier et al.
patent: 5025457 (1991-06-01), Ahmed
patent: 5159281 (1992-10-01), Hedstrom et al.
"A Survey of Digital Phase-Locked Loops" by William C. Lindsey; reprinted from Proc. IEEE, Apr. 1981.

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