Method and apparatus for testing cache RAM residing on a micropr

Details Method and apparatus for testing cache RAM residing on a micropr Method and apparatus for testing cache RAM residing on a micropr

Filed on

1996-09-16

Date issued

1998-07-14

Examiner

Beausoliel, Jr., Robert W.

Other Related Categories

391 212, G11C 2900

Type

Patent

Status

active

Patent number

057817219

Description

ABSTRACT:
An apparatus and method for enabling a cache controller and address and data buses of a microprocessor with an on-board cache to provide a SRAM test mode for testing the on-board cache. Upon assertion of a SRAM test signal to a SRAM test pin on the microprocessor chip, the cache and bus controllers cease normal functionality and permit data to be written to, and read from, individual addresses within the on-board cache as though the on-board cache is simple SRAM. After the chip is reset, standard SRAM tests can then be implemented by reading and writing data to selected cache memory addresses as though the cache memory were SRAM. Upon completion of the tests, the SRAM test signal is deasserted and the cache and bus controllers resume normal operating functionality. A reset signal is then applied to the microprocessor to reinitialize control logic employed within the microprocessor. In this way, cache memory on-board a microprocessor can be tested using standard SRAM testing algorithms and equipment thereby eliminating a need for specialized test equipment to test cache memory contained on a microprocessor chip.

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