Standard cell system large scale integrated circuit with heavy l

Details Standard cell system large scale integrated circuit with heavy l Standard cell system large scale integrated circuit with heavy l

1987-05-15

1989-09-26

Hudspeth, David

Electrical transmission or interconnection systems

Personnel safety or limit control features

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307465, 357 45, H01L 2710

Patent

active

048703001

ABSTRACT:
This invention relates to a standard cell system large scale integrated circuit which comprises arraying a plurality of standard cells that are equally dimensioned in at least one direction and interconnection said standard cells so as to constitute a logic device, whereby the improvement is characterized in that wiring carrying a heavy load and being connected at many places on the surface of the chip is located within each of the standard cells, furthermore said wiring carrying a heavy load and being connected at many places on the surface of the chip is a clock line, and said clock line is located between a power line and a grounding conductor provided within each standard cell.

REFERENCES:
patent: 4590508 (1986-05-01), Hirakawa et al.
Saigo et al., "A Triple-Level Wired 24K-Gate CMOS Gate Array", IEEE JSSC, vol. SC-20, No. 5, Oct. 1985, p. 1005-1010.

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