Error detection and correction method and apparatus for computer

Details Error detection and correction method and apparatus for computer Error detection and correction method and apparatus for computer

1997-08-15

1998-07-14

Baker, Stephen M.

Excavating

371 404, 371 4017, 371 511, G11C 2900, H03M 1300

Patent

active

057815682

ABSTRACT:
An S8ED system is implemented in a memory system to detect single errors involving one or more bits in a byte of subject data, stored in and retrieved from the memory system. Relationships between the subject data and parity data, which are used to detect errors in the subject data, are defined by a novel check matrix. The novel check matrix includes a number of constituent matrices, each of which includes eight (8) vectors. Each vector of a constituent matrix (i) has a number of elements which is equal to the number of parity bits used to detect errors in the subject data; (ii) is a concatenation of a building block vector, one or more instances of one of two base generating vectors, and one or more instances of the other of the two base generating vectors; and (iii) is distinct from all other vectors of the same constituent matrix. Each vector of the check matrix represents check data resulting from a single erroneous bit in either the subject data or the initial parity data and accordingly defines relationships between the subject data and the parity data. These relationships are implemented in error correction code generators to derive parity data from subject data to detect errors in the subject data.

REFERENCES:
patent: H1176 (1993-04-01), Schwoerer
patent: 3697949 (1972-10-01), Carter et al.
patent: 4464753 (1984-08-01), Chen
patent: 4692922 (1987-09-01), Kiriu et al.
patent: 4713816 (1987-12-01), Van Gils
patent: 4888774 (1989-12-01), Kosuge et al.
patent: 5450423 (1995-09-01), Iwasaki et al.
patent: 5535227 (1996-07-01), Silvano
patent: 5550849 (1996-08-01), Harrington
patent: 5563894 (1996-10-01), Fuijwara et al.
patent: 5600659 (1997-02-01), Chen
Reddy, S., "A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems", IEEE Transactions on Computers, vol. C-27, No. 5, May 1978, pp. 455-459.
Kaneda, S., "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications", IEEE Transactions on Computers, vol. C-33, No. 8, Aug. 1984, pp. 737-739.
Dunning, L., "SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems", IEEE Transactions on Computers, vol. C-34, No. 6, Jun. 1985, pp. 557-562.
Fujiwara and Pradhan, "Error-Control Coding in Computers," IEEE Transactions on Computers, Jul. 1990.
Chen, "Error-Correcting Codes with Byte-Detection Capability," IEEE Transactions on Computers. vol. C-32, No. 7, Jul. 1983.
Dunning and Varanasi, "Code Constructions for Error Control in Byte Organized Memory Systems," IEEEE Transactions on Computers, vol. C-32, No. 6, Jun. 1983.
Kaneda and Fujiwara, "Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems," IEEE Transactions on Computers, vol. C-31, No. 7, Jul. 1982.
Vaidya and Pradhan, "A New Class of Bit-and Byte-Error Control Codes,"IEEE Transactions on Information Theory, vol. 38, No. 5, Sep.1992.
Hsiao, "A Class of Optimal Minimum odd-weight-column SEC-DED Codes," IBM Journal of Research and Development, vol. 14, No. 4, Jul. 1970.

Affiliated with

Also associated with

Rating

Error detection and correction method and apparatus for computer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detection and correction method and apparatus for computer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection and correction method and apparatus for computer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1890690