Process for the production of a MIS transistor with a raised sub

Details Process for the production of a MIS transistor with a raised sub Process for the production of a MIS transistor with a raised sub

Filed on

1988-12-15

Date issued

1990-07-03

Examiner

Hearn, Brian E.

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 38, 437 72, 437203, 357233, H01L 21302

Type

Patent

Status

active

Patent number

049391003

Description

ABSTRACT:
A process for the production of a MIS transistor with a rising substrate/gate dielectric interface wall wherein on the surface of a semiconductor substrate having a given doping type is formed a first electrically insulating layer surrounding a zone of the substrate surface. On the first insulating layer and on said zone is formed a second layer. Part of that zone is made to appear by eliminating a fragment of the second layer, which fragment extends above that part, which thus constitutes the bottom of a hole made in the second layer and above part of the first insulating layer. A cavity is formed having at least one rising wall in the bottom of the hole. A third electrically insulating layer is formed on the surface of the aforesaid zone part. On the thus treated surface is formed an electrically conductive layer which eliminated, except in a zone corresponding to the fragment, so as to obtain a transistor gate. The remainder of the second layer is eliminated and the transistor source and drain zones are formed, the drain zone being located on the side of the rising wall.

REFERENCES:
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patent: 4660062 (1987-04-01), Nishizawa et al.
patent: 4685196 (1987-08-01), Lee
patent: 4774206 (1988-09-01), Miller
Ammar, E. S., et al., "UMOS Transistors on (110) Silicon", IEEE Trans. Elec. Dev. Letts., vol. ED-27, No. 5, May 1980, pp. 907-914.
Bampi, et al., "Modified LDD Device Structures for VLSI", IEEE IEDM Tech. Digest, 1985, pp. 234-237.
Ikeda, H., "Substrate Current of Submicrometer Buried-Gate MOSFET," Japanese J. Appl. Phys., vol. 24, No. 6, Jun. 1985, pp. L457-L459.
Takeda, E., et al., "New Grooved-Gate MOSFET with Drain Separated from Channel Implanted Region (DSC)", IEEE Trans. Elect. Dev., vol. ED-30, No. 6, Jun. 1983, pp. 681-686.
Nishimatsu, S., et al., "Grooved Gate MOSFET", Japanses J. Appl. Phys., vol. 16 (1977) Supplement 16-1, pp. 179-183.

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