Process for fabricating isolated vertical bipolar and JFET trans

Details Process for fabricating isolated vertical bipolar and JFET trans Process for fabricating isolated vertical bipolar and JFET trans

1989-09-21

1990-07-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 47, 437 60, 437 76, 357 22, 357 43, 357 51, 357 59, H01L 2980

Patent

active

049390996

ABSTRACT:
A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal
itride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).

REFERENCES:
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patent: 4740821 (1988-04-01), Bertotti et al.
patent: 4806499 (1989-02-01), Shinohara
patent: 4816880 (1989-03-01), Muro

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