Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1996-11-22
1998-07-14
Le, Vu A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523006, G11C 700
Patent
active
057814937
ABSTRACT:
A semiconductor memory device is provided with a first data line pair, second data line pair, a plurality of first bit line pairs respectively connected to the first data line pair through a plurality of first transfer gates, a plurality of second bit line pairs respectively connected to the second data line pair through a plurality of second transfer gates, a plurality of column select lines respectively connected commonly to one first transfer gate and one second transfer gate. A decoder circuit is supplied with an input address and block write signal for activating simultaneously at least two column select lines regardless of the input address while the block write signal is activated, and for activating the column select line corresponding to the input address while the block write signal is inactivated.
REFERENCES:
patent: 5365489 (1994-11-01), Jeong
patent: 5497352 (1996-03-01), Magome
Le Vu A.
NEC Corporation
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