Demultiplexer including a three-state gate

Details Demultiplexer including a three-state gate Demultiplexer including a three-state gate

1991-02-14

1992-12-29

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307473, 307482, 307468, H03K 1920, H03K 19094, H03K 1900

Patent

active

051754460

ABSTRACT:
A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line of a most significant bit bus by a first capacitive device, the control electrode of every transistor is also coupled to one line of a least significant bit bus by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an enable signal the transistor is turned on and current flows from the input terminal to an output node. Each transistor within the demultiplexer thus acts as a three state gate.

REFERENCES:
patent: 4725742 (1988-02-01), Tachimori et al.
patent: 4743899 (1988-05-01), Szeto
patent: 4843261 (1989-06-01), Chappell et al.
patent: 4896302 (1990-01-01), Sato et al.
patent: 4937476 (1990-06-01), Bazes
patent: 4962327 (1990-10-01), Iwazaki
patent: 5021688 (1991-06-01), Leforestier

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