Process for high density flash EPROM cell

Details Process for high density flash EPROM cell Process for high density flash EPROM cell

Filed on

1994-04-25

Date issued

1995-10-24

Examiner

Chaudhuri, Olik

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 48, 437 52, 257315, H01L 21265, H01L 218247

Type

Patent

Status

active

Patent number

054609887

Description

ABSTRACT:
A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.

REFERENCES:
patent: 4975383 (1990-12-01), Baglee
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5049515 (1991-09-01), Tzeng
patent: 5071782 (1991-12-01), Mori
patent: 5135879 (1992-08-01), Richardson
patent: 5141886 (1992-08-01), Mori
patent: 5304503 (1994-04-01), Yoon et al.
"High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", by H. Takato et al, IEDM 1988, pp. 222-224.

Affiliated with

Also associated with

Rating

Process for high density flash EPROM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for high density flash EPROM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for high density flash EPROM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1886282