Memory reference control in a multiprocessor

Details Memory reference control in a multiprocessor Memory reference control in a multiprocessor

1985-06-28

1988-05-17

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1314

Patent

active

047455454

ABSTRACT:
A memory interface and conflict resolution network for a multiprocessor system. The memory is multisectional and each section of memory has a plurality of individually addressable memory banks organized in an interleaved fashion and a section level conflict resolution network. Each processor in the system includes several ports and a gating network such that each port may access any section of memory, but access is restricted to no more than one reference per processor per clock period to each section of memory. References generated from different ports of the same processor are automatically synchronized. Each processor has a conflict resolution circuit to resolve conflicts between different ports seeking access to the same section of memory. Conflict resolution is achieved in two clock periods with conflicts between different ports of a processor resolved in the first clock period and conflicts between different processors seeking access to the same banks of any particular section of memory resolved in the second clock period.

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