Patent
1996-11-29
1998-12-08
Lim, Krisna
395391, G06F 930
Patent
active
058482555
ABSTRACT:
A method and apparatus for increasing the number of instructions which can be utilized by a parallel processor is provided having a group of programmable decode memories used as an operation decoder. When assembling a source file, a decode memory table showing a correspondence between a plural number of given instruction codes and a plural number of control codes is created simultaneously with an execution file. The plural number of instruction codes are input from outside the parallel processor as address signals and written to the group of decode memories via a multiplexer within the parallel processor. In addition, the plural number of control codes are written into the group of decode memories in accordance with the correspondence to the instruction codes contained in the decode memory table.
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Lim Krisna
Mitsubushi Denki Kabushiki Kaisha
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