Boots – shoes – and leggings
Patent
1995-11-06
1998-02-24
Treat, William M.
Boots, shoes, and leggings
364736, G06F 738
Patent
active
057218927
ABSTRACT:
A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.
REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4931980 (1990-06-01), Rault
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5111422 (1992-05-01), Ullrich
patent: 5187679 (1993-02-01), Vassilliadis
patent: 5204828 (1993-04-01), Kohn
patent: 5222037 (1993-06-01), Taniguchi
patent: 5227994 (1993-07-01), Mitsuharu
patent: 5293558 (1994-03-01), Narita et al.
patent: 5420815 (1995-05-01), Nix et al.
patent: 5442799 (1995-08-01), Murakami et al.
patent: 5457805 (1995-10-01), Nakamura
patent: 5487022 (1996-01-01), Simpson et al.
patent: 5506865 (1996-04-01), Weaver, Jr.
patent: 5509129 (1996-04-01), Guttag et al.
patent: 5576983 (1996-11-01), Shiokawa
International Search Report for PCT/US96/12799, Dated Nov. 26, 1996, 1 Page.
J. Shipnes, Graphics Processing with the 88110 RISC Microprocessor, IEEE (1992), pp. 169-174.
MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1991).
Errata to MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1992), pp. 1-11.
MC8810 Programmer's Reference Guide, Motorola Inc. (1992), pp. 1-4.
1860.TM. Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992), Ch. 1, 3, 8, 12.
R. B. Lee, Accelerating Multimedia With Enhanced Microprocessors, IEEE Micro (Apr. 1995), pp. 22-32.
TMS320C2x User's Guide, Texas Instruments (1993) pp. 3-2 through 3-11; 3-28 through 3-34; 4-1 through 4-22; 4-41; 4-103; 4-119 through 4-120; 4-122; 4-150 through 4-151.
L. Gwennap, New PA-RISC Processor Decodes MPEG Video, Microprocessor Report (Jan. 1994), pp. 16, 17.
SPARC Technology Business, UltraSPARC Multimedia Capabilities On-Chip Support for Real-Time Video and Advanced Graphics, Sun Microsystems (Sep. 1994).
Y. Kawakami et al., LSI Applications: A Single-Chip Digital Signal Processor for Voiceband Applications, Solid State Circuits Conference, Digest of Technical Papers; IEEE International (1980).
B. Case, Philips Hopes to Displace DSPs with VLIW, Microprocessor Report (Dec. 94), pp. 12-18.
N. Margulis, i860 Microprocessor Architecture, McGraw Hill, Inc. (1990) Ch. 6, 7, 8, 10, 11.
Pentium Processor User's Manual, vol. 3; Architecture and Programming Manual, Intel Corporation (1993), Ch. 1, 3, 4, 6, 8, and 18.
Dulong Carole
Eitan Benny
Kowashi Eiichi
Mennemeier Larry M.
Mittal Millind
Intel Corporation
Maung Zarni
Treat William M.
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