Patent
1995-11-30
1998-02-24
Butler, Dennis M.
395309, 395559, G06F 112
Patent
active
057218862
ABSTRACT:
A synchronizer circuit which bypasses synchronous clock signals or maintains synchronicity of synchronous clock signals without degrading system performance. The synchronizer circuit includes a synchronizer having first and second clock signal inputs. A switching circuit couples to the first clock signal and to the output of the synchronizer. The synchronizer circuit is preferably programmable, and includes a control circuit which determines whether the first and second frequencies are synchronous or asynchronous, which causes the switching circuit to select the synchronizer output when the first and second frequencies are asynchronous, and which causes the switching circuit to select the first clock signal when the first and second frequencies are synchronous. The switching circuit may also couple to a first stage output of the synchronizer, and the control circuit may cause the switching circuit to select the first stage output when the first and second frequencies are synchronous and either of the first and second frequencies is a multiple of the other. The switching circuit may also include logic elements for decoupling the first and second clock signals from a multi-frequency device when the first and second frequencies are changing.
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Butler Dennis M.
Martin Paul W.
NCR Corporation
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