Method for fabricating MOS transistors having gates with differe

Details Method for fabricating MOS transistors having gates with differe Method for fabricating MOS transistors having gates with differe

1987-03-30

1988-05-17

Roy, Upendra

Fishing, trapping, and vermin destroying

148DIG82, 357 235, 357 2314, 437 45, 437 46, 437157, H01L 21265

Patent

active

047450797

ABSTRACT:
A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

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