Patent
1996-07-12
1998-02-24
Lall, Parshotam S.
395393, G06F 938
Patent
active
057218552
ABSTRACT:
A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages.
The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results. In one embodiment, the instructions are executed by determining the data readiness of each of the operations and scheduling data ready operations. These scheduled data ready operations are dispatched to an execution unit and executed. The results are written back for use by other operations or as data output or indication. The determination of execution readiness, the dispatching and the execution, and writeback, are performed in consecutive pipestages.
The present invention also provides for retiring each of the continuous stream of operations in such a manner as to commit their results to architectural state and to reestablish sequential program order.
REFERENCES:
patent: 4722049 (1988-01-01), Lahti
patent: 4773041 (1988-09-01), Hassler et al.
patent: 4791557 (1988-12-01), Angel et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5185871 (1993-02-01), Frey et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5280615 (1994-01-01), Church et al.
patent: 5323489 (1994-06-01), Bird
patent: 5355457 (1994-10-01), Shebanow et al.
patent: 5363495 (1994-11-01), Fry et al.
patent: 5377341 (1994-12-01), Kaneko et al.
patent: 5463745 (1995-10-01), Vidwans et al.
patent: 5471633 (1995-11-01), Colwell et al.
patent: 5548776 (1996-08-01), Colwell et al.
patent: 5553256 (1996-09-01), Fetterman et al.
patent: 5651125 (1997-07-01), Witt et al.
Mike Johnson; Superscalar Microprocessor Design; pp. 127-133, 139-142, 146, 199-200; 1991.
Popescu, Val; Schultz, Merle; Spracklen, John; Gibson, Gary; Lightner, Bruce; Isaman, David, "The Metaflow Architecture", IEEE Micro, Jun. 1991, p. Nos. 10-13 and 63-73.
Johnson, Mike, "Superscalar Microprocessor Design", Englewood Cliffs, N.J.,:Prentice-Hall, 1991 (only table of contents).
Colwell Robert P.
Fetterman Michael A.
Glew Andrew F.
Hinton Glenn J.
Papworth David B.
Coulter Kenneth R.
Intel Corporation
Lall Parshotam S.
LandOfFree
Method for pipeline processing of instructions by controlling ac does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for pipeline processing of instructions by controlling ac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for pipeline processing of instructions by controlling ac will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1880778