System for determining occurrence sequence of sampled data

Excavating

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364480, 364900, 371 29, G06F 1520

Patent

active

047486244

ABSTRACT:
In a logic analyzer including first and second sampling channels operative with different clocks independently, a system for determining sequence in time in which the sampled data are generated in both sampling channels includes a memory interposed between the first and second sampling channels. The memory has a data input supplied with the address data of the first sampling channel, an address input supplied with the address data of the second sampling channel and a data write input supplied with the clock signal of the second sampling channel.

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