Performing tree additions via multiplication

Details Performing tree additions via multiplication Performing tree additions via multiplication

1996-05-17

1998-02-24

Ngo, Chuong Dinh

Boots, shoes, and leggings

364758, 364784, 364786, G06F 750, G06F 752

Patent

active

057216975

ABSTRACT:
A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree addition is performed. A second value is input into the multiplier in place of a second multiplicand. Each bit of the second value is at logic zero except for a first subset of bits. The first subset of bits are bits of the second value, starting with the low order bit, which are at intervals equal to a bit length of each addend. Each of the first subset of bits is set to logic one. In partial product rows in the multiplier which correspond to the first subset of bits, certain partial products are forced to logic zero. This is done in such a way that all the addends for the tree addition are aligned in columns of the multiplier. The partial products are then summed to produce a result.

REFERENCES:
patent: 4369500 (1983-01-01), Fette
patent: 4736335 (1988-04-01), Barkan
patent: 5095457 (1992-03-01), Jeong

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