Semiconductor memory device with redundancy circuits

Details Semiconductor memory device with redundancy circuits Semiconductor memory device with redundancy circuits

1986-09-16

1988-05-31

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365189, 365200, 307449, G11C 700, G11C 800

Patent

active

047485973

ABSTRACT:
Address signals are decoded by partial decoders, to generate in-phase and complementary signals. These signals are selectively input to main decoders consisting of NAND circuits. Further, these signals are fed via through programming fuse elements to a NOR gate. The fuse elements and the NOR gate form a programmable spare decoder. When the bit selected by the main decoder is defective, the output of this main decoder is shut off. Further, the fuse element of the spare decoder is opened corresponding to the main decoder to select the defective bit, thereby to replace the defective bit with the spare bit.

REFERENCES:
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patent: 4654830 (1987-03-01), Chua et al.
patent: 4658379 (1987-04-01), Fujishima et al.
Canker et al., "A Fault-Tolerant 64K Dynamic RAM," IEEE International Solid-State Circuits Conference, ISCC, pp. 150-151 and 290, Feb. 15, 1979.

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