Video memory control apparatus

Details Video memory control apparatus Video memory control apparatus

1987-01-20

1988-05-31

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 22, 358160, 358183, 340721, 340749, H04N 708, H04N 5262

Patent

active

047485043

ABSTRACT:
The video memory control apparatus of the present invention has the first and second counters for repetitiously counting the clock signal at an interval of the display cycle period. The second counter is reset by an external synchronization signal. The first counter is reset by the counter reset signal supplied from the counter reset signal generator circuit. The counter reset signal is used to continue resetting the first counter from when the first counter terminates counting the display cycle period to when the second counter terminates counting the display cycle period. When an external synchronization with a phase shift is inputted, the first counter is kept reset by the counter reset signal for a period corresponding to the phase shift of the external synchronization signal. Consequently, in a case of the superimpose display, even if the external synchronization signal undergoes a phase shift, the synchronization can be established again in a short period of time.

REFERENCES:
patent: 4218710 (1980-08-01), Kashigi et al.
patent: 4626837 (1986-12-01), Priestly

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