Method and apparatus for interrupt signaling in a computer syste

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364941, 364DIG2, G06F 1324

Patent

active

055354203

ABSTRACT:
A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.

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