Parallel processor having decoder for selecting switch from the

Details Parallel processor having decoder for selecting switch from the Parallel processor having decoder for selecting switch from the

1994-11-08

1996-07-09

An, Meng-Al

Boots, shoes, and leggings

3642283, 3642287, 364229, 3642292, 3642319, 364DIG1, 395163, G06F 1300

Patent

active

055354106

ABSTRACT:
A parallel processor utilizing a memory cell array for rapidly performing parallel processing by switching between SIMD and MIMD operations depending on the type of problems to be solved. Where SIMD and MIMD operations are mixed in an application, the time loss in the switching therebetween is eliminated so as to enhance the speed of the processing. The parallel processor comprises a two-dimensional memory array for storing data to be operated on; a transfer network for transferring to a group of processing elements the data read in parallel from word lines connected to memory cells in the two-dimensional memory array, the group of processing elements performing parallel processing on the data transferred thereto; signal lines for transmitting an instruction in a SIMD operation mode; an instruction buffer for storing and forwarding parallelly instructions in a MIMD operation mode; and a group of switches for switching between the SIMD and the MIMD operation mode.

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Howard Jay Siegel; "Aspects of Mapping Tanks Onto Parallel Processing Systems" 11-13/Sep. 1991, IEEE.

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