Microprocessor status register having plural control information

Details Microprocessor status register having plural control information Microprocessor status register having plural control information

1993-12-21

1996-07-09

Pan, Daniel H.

Boots, shoes, and leggings

364DIG1, 364DIG2, 395550, 395750, 39518222, 327210, 327291, G06F 106, G06F 124, G06F 9308

Patent

active

055354041

ABSTRACT:
A status register apparatus includes a control information register for holding one item of control information. An ON decoder is connected to receive a control word composed of a plurality of bits and for generating a set signal to the control information register when the ON decoder detects a first bit pattern for setting the control information register into an on condition. An OFF decoder is connected to receive the control word and for generating a clear signal to the control information register when the OFF decoder detects a second bit pattern for setting the control information register into an off condition. When the first bit pattern is detected by the ON decoder, the control information register is set to the on condition in response to the set signal. When the second bit pattern is detected by the OFF decoder, the control information register is set to the off condition in response to the clear signal. When neither the first bit pattern nor the second bit pattern is detected, the control information register maintains its preceding condition.

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"Structured Computer Organization", pp. 58-112, Chapter 3, 1984 by Prentice Hall, N.J., Andrew Tanenbaum.
Tanenbaum, Adrew, S., Structured Computer Org. pp. 58-97, Prentice Hall 1984 N.J.
Gschwind et al.; Design of Digital Computers; pp. 123-141. 1975; NY.

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