Boots – shoes – and leggings
Patent
1994-01-31
1996-07-09
Kriess, Kevin A.
Boots, shoes, and leggings
364270, 364271, 3642711, 364DIG1, G06F 112
Patent
active
055353770
ABSTRACT:
A method and apparatus which synchronizes signals operating at different clock speeds with reduced synchronization latency. The present invention is preferably used in systems where a first logic portion operating at a first clock speed, referred to as a fast clock speed, interfaces to a second logic portion operating at a second, slower clock speed. A new slow clock is generated pseudo-synchronously from the fast clock using a phase locked loop (PLL) clock generator. The PLL multiplies the fast clock frequency up to the least common multiple (LCM) of the two frequencies to generate a base clock signal. The base clock is then divided down to form the slow clock signal. The PLL performs its operations in such a way that all three clocks have a fixed phase relationship. The rising edges of the base clock, fast clock, and slow clock line up at periodic points and are skewed at other periodic points. Fast to slow synchronization logic and slow to fast synchronization logic are included which synchronize signals travelling between the logic portions. In the general case for a first logic portion having a fast clock frequency m and a second logic portion having a slow clock frequency n, the base clock frequency would be the LCM (m,n). The multiplexor in the slow to fast signal synchronization logic used to synchronize slow signals, i.e., signals from the second logic portion, to the faster clock frequency would have .sup.base clock /.sub.m inputs. The multiplexor used to synchronize fast signals to the slower clock speed would have .sup.base clock /.sub.n inputs. Therefore, a method and apparatus for synchronizing signals travelling between logic portions based on different clock speeds is disclosed. This method has reduced latency as compared to prior art methods and thus provides increased performance over prior art designs.
REFERENCES:
patent: 4405898 (1983-09-01), Flemming
patent: 5077686 (1991-12-01), Rubinstein
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5256994 (1993-10-01), Langendorf
patent: 5345109 (1994-09-01), Mehta
Butler Dennis M.
Dell USA L.P.
Garrana Henry N.
Kahler Mark P.
Kriess Kevin A.
LandOfFree
Method and apparatus for low latency synchronization of signals does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for low latency synchronization of signals , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for low latency synchronization of signals will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1876222