Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-09-30
1999-05-04
Hoang, Huan
Static information storage and retrieval
Addressing
Sync/clocking
36518905, 365194, G11C 800
Patent
active
059011092
ABSTRACT:
A semiconductor memory device includes a memory array for outputting data stored in a memory cell at an address corresponding to an address signal generated according to an address control signal synchronized with a clock pulse, a data reading circuit for reading a data signal outputted from the memory array, an activation signal generating circuit for receiving a delay signal generated based on the address signal and generating an activation signal for activating the data reading circuit to read the data signal outputted from the memory array into the data reading circuit, and a data output circuit for outputting a data signal outputted from the data reading circuit according to the input of an output enable signal synchronized with the clock pulse.
REFERENCES:
patent: 5668774 (1997-09-01), Furutani
patent: 5703829 (1997-12-01), Suzuki et al.
patent: 5708614 (1998-01-01), Koshikawa
patent: 5748560 (1998-05-01), Sawada
Yukinori Kodama et al., "A 150-MHz 4-Bank 64M-bit SDRAM with Address Incrementing Pipeline Scheme," 1994 Symposium on VLSI Circuits Digest of Technical Papers; pp. 81-82.
Hoang Huan
OKI Electric Industry Co., Ltd.
LandOfFree
Semiconductor memory device capable of higher-speed operation an does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device capable of higher-speed operation an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of higher-speed operation an will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1874933