Pipelined fast-access floating gate memory architecture and meth

Details Pipelined fast-access floating gate memory architecture and meth Pipelined fast-access floating gate memory architecture and meth

1996-12-26

1999-05-04

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518525, 365203, 365205, G11C 1604

Patent

active

059010860

ABSTRACT:
A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

REFERENCES:
patent: 4893278 (1990-01-01), Ito
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5592435 (1997-01-01), Mills et al.
patent: 5604701 (1997-02-01), Alexander et al.
patent: 5657292 (1997-08-01), McClure
patent: 5784705 (1998-07-01), Leung

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