Priority processing of ATM cells using shift register stages

Details Priority processing of ATM cells using shift register stages Priority processing of ATM cells using shift register stages

Filed on

1995-03-08

Date issued

1996-07-09

Examiner

Kizou, Hassan

Patent Class

Multiplex communications

SubClass

Wide area network

SubSubClass

Packet switching

Other Related Categories

370 856, H04L 1256

Type

Patent

Status

active

Patent number

055352022

Description

ABSTRACT:
In order to obtain a buffer control shift register for an ATM switching unit for transmitting ATM cells which are stored in the unit while controlling the same in response to deadlines thereof, the unit comprises a comparator (53) for comparing dispatch times DPT.sub.0 of inputted ATM cells with those stored in a register (51). Registers (50, 51) are formed to be capable of bidirectional shifting (positive and negative directions along .gamma.). A shift/write control (54) rearwardly shifts data having a larger dispatch time in response to the result of comparison of the comparator (53), to write data of the inputted ATM cells in the vacated portion. It is possible to sequence data of the shift register from the frontmost stage in order of the dispatch times.

REFERENCES:
patent: 5166926 (1992-11-01), Cisneros et al.
patent: 5166930 (1992-11-01), Braff et al.
patent: 5184346 (1993-02-01), Kozaki et al.
patent: 5233606 (1993-08-01), Pashan et al.
Proceeding of the 1990 International Switching Symposium, May 21-Jun. 1, 1990, pp. 21-26, vol. V, Takeo Koinuma, et al., "AN ATM SWITCHING SYSTEM BASED ON A DISTRIBUTED CONTROL ARCHITECTURE".
IEEE Journal of Solid-State Circuits, vol. 27, No. 7, Jul. 1992, pp. 1116-1120, Alain Chemarin, et al., "A HIGH-SPEED CMOS CIRCUIT FOR 1.2-Gb/s 16 .times. 16 ATM SWITCHING".
1990 Symposium on VLSI Circuits, 1990, pp. 109-110, Ichiro Okabayashi, et al., "A PROPOSED STRUCTURE OF A 4MBIT CONTENT-ADDRESSABLE AND SORTING MEMORY".

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