Delay model abstraction

Details Delay model abstraction Delay model abstraction

Filed on

1995-02-03

Date issued

1996-07-09

Examiner

Teska, Kevin J.

Patent Class

Boots, shoes, and leggings

Other Related Categories

364488, 395500, G06F 1750

Type

Patent

Status

active

Patent number

055351450

Description

ABSTRACT:
An abstracted delay model for a circuit network is generated wherein each internal node and connecting edges of an inputted detailed delay graph are processed. All delay edges in the delay graph which could contribute to an extreme delay path from some primary input of the delay graph are marked as necessary. Unnecessary edges are then removed to produce a partially abstracted delay graph. For each internal node in the partially abstracted delay graph, in-edges and out-edges of the node are then merged, if merging does not cause an increase in the number of edges in the delay graph, thus reducing the total number of edges in the delay abstraction.

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