Method of fabricating junction field effect transistors

Details Method of fabricating junction field effect transistors Method of fabricating junction field effect transistors

1984-03-29

1985-11-12

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148187, H01L 21265

Patent

active

045519099

ABSTRACT:
Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface. The device exhibits both high voltage gain and low gate capacitance.

REFERENCES:
patent: 3828230 (1974-08-01), Nishizawa et al.
patent: 4199771 (1980-04-01), Nishizawa et al.
patent: 4406052 (1983-09-01), Cogan
patent: 4437925 (1984-03-01), Cogan
patent: 4442589 (1984-04-01), Doo et al.
patent: 4449284 (1984-05-01), Shimbo
patent: 4477963 (1984-10-01), Cogan
patent: 4497107 (1985-02-01), Cogan
Cogan et al., Proceedings of the International Electron Devices Meeting (IEEE), Dec. 5-7, 1983, Wn., D.C., Paper 95, pp. 221-224.

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