Process for fabricating a semiconductor device

Details Process for fabricating a semiconductor device Process for fabricating a semiconductor device

1983-11-23

1985-11-12

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29589, 148 15, 357 67, 357 71, 427 88, 427 93, H01L 2124, H01L 2128

Patent

active

045519072

ABSTRACT:
A metal silicide interconnection technique selectively forming a metal silicide layer on a silicon layer followed by heat treating the layers so that a surface silicon dioxide layer is formed and the metal silicide layer is forced down and is buried under the silicon dioxide layer. This silicon dioxide layer has an even top surface.

REFERENCES:
patent: 3777364 (1973-12-01), Schinella et al.
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4285761 (1981-08-01), Fatula et al.
patent: 4332839 (1982-06-01), Levinstein et al.
Laibowitz et al., "Fabrication of Vias in a Multilayered Metallization in LSI Technology"; IBM Tech. Disc. Bull., vol. 21, No. 12, May 1979, pp. 5051-5052.
Shibata et al.; "Metal Silicon Reactions Induced by CW Scanned Laser and Electron Beams", J. Electrochem Soc.; vol. 128, No. 3, Mar. 1981, pp. 637-644.
Howard; "Gate for MOS Devices: Rare Earth Silicides"; IBM Tech. Disc. Bul., vol. 21, No. 7, Dec. 1978, pp. 2811-2813.
Rideout; "Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits", IBM Tech. Disc. Bul., vol. 17, No. 6, Nov. 1974, pp. 1831-1833.

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