Synchronous bus lock mechanism permitting bus arbiter to change

Details Synchronous bus lock mechanism permitting bus arbiter to change Synchronous bus lock mechanism permitting bus arbiter to change

1989-07-03

1992-06-30

Eng, David Y.

Boots, shoes, and leggings

3642426, 36424292, 364240, 3642407, 364DIG1, 395800, G06F 1342

Patent

active

051270897

ABSTRACT:
A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

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patent: 4730268 (1988-03-01), Marin
patent: 4791562 (1988-12-01), Shima
patent: 4908749 (1990-03-01), Marshall et al.
patent: 4947368 (1990-08-01), Donaldson et al.

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