1990-06-06
1992-06-30
Smith, Jerry
Excavating
371 211, 371 221, G01R 3128
Patent
active
051270102
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present relates to a pattern generator which generates patterns for testing logic circuits as well as for memories.
2. The Related Art
Heretofore, an algorithmic pattern generator has been used to generate patterns for testing semiconductor memories as disclosed in U.S. Pat. No. 4,293,950 or 4,797,886, for instance. In the conventional algorithmic pattern generator an instruction memory 12 is accessed using an address produced by a program counter, as schematically shown in FIG. 1. The instruction memory 12 is composed of an operation code field 13 which has stored therein instructions for JUMP, LOOP and other operations, an operand field 14 in which is stored an operand such as a loop count corresponding to, for example, the LOOP instruction of the operation code field 13, and a field 15 in which an address computing instruction, a data computing instruction and a control signal are stored. These fields 13, 14 and 15 are simultaneously read out at each address. The instruction from the operation code field 13 is decoded by an instruction decoder 16, by which the value of a program counter 11 is modified to, for example, a jump address of the JUMP instruction. In response to the instructions read out of the field 15, an arithmetic unit 17 generates an address pattern AP which is applied to a memory under test (not shown), a data pattern DP which is written into the memory under test and an expectation pattern EP of data which is output from the memory under test. Further, the arithmetic unit responds to the control signal from the field 15 to generate a write instruction and an instruction for comparison with the expectation pattern.
With the recent progress of semiconductor technology, there has emerged a memory for specific use which has incorporated therein a large number of logic circuits instead of providing therearound control circuits, as in normal memories.
Test patterns and expectation patterns for logic circuits are random patterns in many cases, and it has been considered impossible to employ the conventional algorithmic pattern generator for the generation of such random patterns, because it requires therefore an instruction memory of a storage capacity large enough to store an enormous number of instruction steps.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a pattern generator which permits algorithmic generation of patterns for testing memories and the generation of random patterns for logic tests with simple instruction steps.
According to the present invention, patterns for testing random logic (logic circuits) are stored in a data buffer memory, which is accessed by an address pointer, address data for setting arbitrary address data in the address pointer is held in a load data memory, and load/increment control data for the address pointer is held in a control instruction memory. The load data memory and the control instruction memory are concurrently accessed from a program counter.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a conventional pattern generator;
FIG. 2 is a block diagram illustrating an embodiment of the pattern generator of the present invention; and
FIG. 3 is a timing chart for explaining the operation of the embodiment depicted in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 2 illustrates an embodiment, in which the parts corresponding to those in FIG. 1 are identified by the same reference numerals. In the present invention a data buffer memory 18 is provided, in which random logic patterns for testing random logic (logic circuits) are stored at respective addresses. The data buffer memory 18 is accessed using the output value of an address pointer 19 as an address.
In this embodiment the instruction memory 12' further includes a load data field 21 and a control instruction field 22 at each address. Address data to be set in the address pointer 19 is written into the load data field 21. Load/increment control instruction data for the address point
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Advantest Corporation
Hua Ly V.
Smith Jerry
LandOfFree
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