Patent
1996-01-05
1998-06-30
Butler, Dennis M.
395559, G06F 108
Patent
active
057747032
ABSTRACT:
A data processing system having register controllable processor speed includes a central processor (110) which operates at a selectable address bus clock speed (122) and subsystem components (115) also having selectable speeds. Subsystem clock provision conductors (124) independently provide a selectable subsystem clock speed for each of the subsystem components. Addressable registers (200, 250, 300) store a plurality of optimum address bus clock speed and subsystem clock speed values. A selector circuit (137, 138) reads a first addressable register to provide the optimum speed value for use as the selectable address bus clock speed of the central processor and reads a second addressable register to provide the optimum speed value for use as the selectable subsystem clock speed of a first subsystem clock component.
REFERENCES:
patent: 4615005 (1986-09-01), Maejima et al.
patent: 4686386 (1987-08-01), Tadao
patent: 4893271 (1990-01-01), Davis et al.
patent: 5155840 (1992-10-01), Niijima
patent: 5205387 (1993-04-01), Frane
patent: 5222239 (1993-06-01), Rosch
patent: 5247655 (1993-09-01), Khan et al.
patent: 5432468 (1995-07-01), Moriyama et al.
patent: 5537581 (1996-07-01), Conary et al.
Shemelynce John Nicholas
Weiss Karl Robert
Argon Juliana
Butler Dennis M.
King Robert L.
Motorola Inc.
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