Central processing unit detecting and judging whether operation

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395390, 395391, 395392, G06F 900

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active

057746877

ABSTRACT:
A central processing unit in a microprocessor, or the like, executes at high speed a simple program and sets a different immediate depending on a true or false state of a predetermined condition. In the central processing unit, the first and second immediates are set in the instruction code, which is prefetched by an instruction queue. Depending on whether a value of one or zero is stored in the zeroflag, which corresponds to the true or false state of the predetermined condition, the first or second immediate is written into an address location of the register or the memory designated by the same instruction code.

REFERENCES:
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patent: 5177701 (1993-01-01), Iwasa
patent: 5193167 (1993-03-01), Sites et al.
patent: 5410682 (1995-04-01), Sites et al.
patent: 5537560 (1996-07-01), Boggs et al.
patent: 5568624 (1996-10-01), Sites et al.
A fine-grained MIMD architecture based upon register channels by Gupta, 1992 IEEE publication, pp. 28-37, Nov. 1992.

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